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2001 ieee1394 ohci 1.1 compliant 3port phy-link 1-chip host controller preliminary data sheet mos integrated circuit pd72874 document no. s15306ej2v0ds00 (2nd edition) date published april 2002 ns cp (k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the pd72874 is the lsi that integrated ohci-link and phy function into a single chip. the pd72874 complies with the 1394 ohci specification 1.1 and the ieee std 1394a-2000 specifications, and works up to 400 mbps. it makes design so compact for pc and pc card application. features ? compliant with link layer services as defined in 1394 open host controller interface specification release 1.1 compliant with physical layer services as defined in ieee std 1394a-2000 provides three cable ports at 100/200/400 mbps super low power consumption for physical layer compliant with protocol enhancement as defined in ieee std1394a-2000 modular 32-bit host interface compliant to pci specification release 2.2 supports pci-bus power management interface specification release 1.1 modular 32-bit host interface compliant to card bus specification cycle master and isochronous resource manager capable built-in fifos for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072 bytes) supports d0, d1, d2, d3hot supports wake up function from d3cold 32-bit crc generation and checking for receive/transmit packets 4 isochronous transmit dmas and 4 isochronous receive dmas supported 32-bit dma channels for physical memory read/write clock generation by 24.576 mhz x?tal 2-wire serial eeprom tm interface supported separate power supply link and phy programmable latency timer from serial eeprom in cardbus mode (card_on = 1) ordering information part number package pd72874gc-yeb 120-pin plastic tqfp (fine pitch) (14 x 14) the mark shows major revised points.
preliminary data sheet s15306ej2v0ds 2 pd72874 firewarden? roadmap ieee1394-1995 core development firewarden series ohci link pd72860 ohci link pd72861 1-chip ohci+phy pd72872 ohci link pd72862 1-chip ohci+phy pd72870 1-chip ohci+phy pd72870a, 72870b 1-chip ohci 1.1+phy pd72874 1-chip ohci 1.1+phy pd72873 link core
preliminary data sheet s15306ej2v0ds 3 pd72874 block diagrams link core state machine logic pci controller it fifo at fifo ir fifo power management controller csr register phy interface dma controller comand fifo pci configuration register pme ad0 to ad31 cbe0 to cbe3 frame req gnt irdy trdy devsel stop inta par idsel clkrun perr serr prst pclk rsmrst d3csup pci interface i/o rom interface i/o grom_en grom_scl grom_sda card_on arbitration and control state machine logic link interface receive data decoder and retimer transmit data encoder voltage and current generator crystal oscillator pll system and transmit clock generator cable power status cps pc0 pc1 pc2 tpa0p tpa0n tpb0p tpb0n tpa1p tpa1n tpb1p tpb1n tpa2p tpa2n tpb2p tpb2n cable port0 cable port1 cable port2 tpbias 0 tpbias1 tpbias 2 r0 r1 xo xi p_reset l_v dd pci_v dd p_dv dd p_av dd gnd gnd link block phy block
preliminary data sheet s15306ej2v0ds 4 pd72874 pin configuration (top view) ? 120-pin plastic tqfp (fine pitch) (14 x 14) pd72874gc-yeb l_v dd clkrun pme inta prst pclk gnt req gnd ad31 ad30 ad29 ad27 ad26 ad25 ad28 ad24 l_v dd gnd cbe3 idsel ad23 ad22 ad21 ad20 gnd ad19 ad18 pci_v dd l_v dd gnd xo xi p_av dd ic(n) gnd gnd p_dv dd ic(l) p_reset l_v dd ic(l) ic(h) rsmrst p_dv dd pc2 pc1 pc0 gnd ic(l) p_dv dd 90 89 88 86 85 84 83 87 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 62 63 61 ad4 pci_v dd gnd cbe2 gnd stop ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 l_v dd cbe0 ad7 ad6 ad17 ad16 frame irdy l_v dd trdy devsel gnd 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 44 49 50 51 52 53 54 55 56 57 58 59 60 perr serr par l_v dd cbe1 gnd 120 119 118 116 115 114 113 117 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 92 93 91 tpa2p p_av dd tpbias2 card_on ic(l) d3csup tpa2n ri1 tpb2n gnd tpa1p tpa1n tpb1p tpb1n tpa0p tpa0n tpb0p tpb0n tpbias1 tpbias0 p_av dd gnd ri0 tpb2p 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 14 19 20 21 22 23 24 25 26 27 28 29 30 grom_sda grom_scl grom_en ad0 ad1 ad2 ad3 gnd gnd ad5 p_av dd cps ic(l)
preliminary data sheet s15306ej2v0ds 5 pd72874 pin name ad0 to ad31 : pci multiplexed address and data card_on : pci/card select cbe0 to cbe3 : command/byte enables clkrun : pciclk running cps : cable power status input d3csup : d3cold support devsel : device select frame : cycle frame gnd : gnd gnt : bus_master grant grom_en : serial eeprom enable grom_scl : serial eeprom clock output grom_sda : serial eeprom data input / output ic(h) : internally connected (high clamped) ic(l) : internally connected (low clamped) ic(n) : internally connected (open) idsel : id select inta : interrupt irdy : initiator ready l_v dd : v dd for link digital core and link i/os par : parity pc0 to pc2 : power class input pci_v dd : v dd for pci i/os pclk : pci clock perr : parity error pme : pme output prst : reset p_av dd : phy analog v dd p_dv dd : phy digital v dd p_reset : phy power on reset input req : bus_master request ri0 : resistor0 for reference current setting ri1 : resistor1 for reference current setting rsmrst : resume reset serr : system error stop : pci stop tpa0n : port-1 twisted pair a negative input/output tpa0p : port-1 twisted pair a positive input/output tpa1n : port-2 twisted pair a negative input/output tpa1p : port-2 twisted pair a positive input/output tpa2n : port-3 twisted pair a negative input/output tpa2p : port-3 twisted pair a positive input/output tpb0n : port-1 twisted pair b negative input/output tpb0p : port-1 twisted pair b positive input/output tpb1n : port-2 twisted pair b negative input/output tpb1p : port-2 twisted pair b positive input/output tpb2n : port-3 twisted pair b negative input/output tpb2p : port-3 twisted pair b positive input/output tpbias0 : port-1 twisted pair bias voltage output tpbias1 : port-2 twisted pair bias voltage output tpbias2 : port-3 twisted pair bias voltage output trdy : target ready xi : x?tal xi xo : x?tal xo
preliminary data sheet s15306ej2v0ds 6 pd72874 contents 1. pin functions............................................................................................................. ........................ 8 1.1 pci/cardbus interface signals: (52 pins) .................................................................................. .... 8 1.2 phy signals: (20 pins) .................................................................................................... .............. 10 1.3 phy control signals: (4 pins)............................................................................................. .......... 10 1.4 pci/cardbus select signal: (1 pin)........................................................................................ ....... 10 1.5 serial rom interface signals: (3 pins).................................................................................... ..... 11 1.6 d3cold wake up function signals: (2 pins) ............................................................................... 11 1.7 ic: (7 pins) .............................................................................................................. ........................ 11 1.8 v dd ............................................................................................................................... .................... 12 1.9 gnd....................................................................................................................... .......................... 12 2. phy registers.............................................................................................................. ..................... 13 2.1 complete structure for phy registers...................................................................................... .. 13 2.2 port status page (page 000)............................................................................................... .......... 16 2.3 vendor id page (page 001) ................................................................................................. .......... 17 2.4 vendor dependent page (page 111 : port_select 0001) ............................................................ 17 3. configuration registers ................................................................................................... ....... 18 3.1 pci bus mode configuration register (card_on = low)........................................................ 18 3.1.1 offset_00 vendor id register ......................................................................................... .................. 19 3.1.2 offset_02 device id register......................................................................................... ................... 19 3.1.3 offset_04 command register ........................................................................................... ................ 19 3.1.4 offset_06 status register ............................................................................................ ..................... 20 3.1.5 offset_08 revision id register ....................................................................................... .................. 21 3.1.6 offset_09 class code register........................................................................................ ................. 21 3.1.7 offset_0c cache line size register................................................................................... .............. 21 3.1.8 offset_0d latency timer register ..................................................................................... ............... 21 3.1.9 offset_0e header type register ....................................................................................... ............... 21 3.1.10 offset_0f bist register .............................................................................................. .................... 21 3.1.11 offset_10 base address 0 register ................................................................................... ............. 22 3.1.12 offset_2c subsystem vendor id register .............................................................................. ........ 22 3.1.13 offset_2e subsystem id register..................................................................................... .............. 22 3.1.14 offset_34 cap_ptr register .......................................................................................... .................. 22 3.1.15 offset_3c interrupt line register................................................................................... ................. 22 3.1.16 offset_3d interrupt pin register .................................................................................... ................. 23 3.1.17 offset_3e min_gnt register .......................................................................................... ................. 23 3.1.18 offset_3f max_lat register .......................................................................................... ................. 23 3.1.19 offset_40 pci_ohci_control register ................................................................................. .......... 23 3.1.20 offset_60 cap_id & next_item_ptr register ........................................................................... ....... 23 3.1.21 offset_62 power management capabilities register.................................................................... .. 24 3.1.22 offset_64 power management control/status register.................................................................. 25 3.2 cardbus mode configuration register (card_on = high)...................................................... 26 3.2.1 offset_14/18 base address 1/2 register (cardbus status registers).............................................. 27 3.2.2 offset_28 cardbus cis pointer........................................................................................ ................. 28 3.2.3 offset_80 cis area ................................................................................................... ........................ 28
preliminary data sheet s15306ej2v0ds 7 pd72874 4. phy function.............................................................................................................. ...................... 29 4.1 cable interface........................................................................................................... .................... 29 4.1.1 connections ............................................................................................................. ............................ 29 4.1.2 cable interface circuit................................................................................................. ......................... 30 4.1.3 cps ..................................................................................................................... ................................. 30 4.1.4 unused ports............................................................................................................ ............................ 30 4.2 pll and crystal oscillation circuit ....................................................................................... ...... 30 4.2.1 crystal oscillation circuit ............................................................................................. ........................ 30 4.2.2 pll ..................................................................................................................... .................................. 30 4.3 pc0 to pc2 ................................................................................................................ ..................... 30 4.4 p_reset ................................................................................................................... ..................... 30 4.5 ri0, ri1 .................................................................................................................. ......................... 30 5. electrical specifications................................................................................................. ........ 31 6. package drawing ........................................................................................................... ............... 34 7. recommended soldering conditions................................................................................... 35
preliminary data sheet s15306ej2v0ds 8 pd72874 1. pin functions 1.1 pci/cardbus interface signals: (52 pins) (1/2) name i/o pin no. i ol volts(v) function block * par i/o 44 pci/cardbus 5/3.3 parity is even parity across ad0 to ad31 and cbe0 to cbe3. it is an input when ad0 to ad31 is an input; it is an output when ad0 to ad31 is an output. link ad0 to ad31 i/o 9, 10, 12, 13, 15 to18, 23, 24, 26 to 29, 32, 33, 47 to 50, 52, 53, 55, 56, 58, 59, 62, 63, 65 to 68 pci/cardbus 5/3.3 pci multiplexed address and data link cbe0 to cbe3 i/o 21, 34, 45, 57 - 5/3.3 command/byte enables are multiplexed bus commands & byte enables. link frame i/o 35 pci/cardbus 5/3.3 frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. if car dbus mode (card_on = 1), this pin should be pulled up to v dd . link trdy i/o 37 pci/cardbus 5/3.3 target ready indicates that the current data phase of the transaction is ready to be completed. link irdy i/o 36 pci/cardbus 5/3.3 initiator ready indicates that the current bus master is ready to complete the current data phase. during a write, its assertion indicates that the initiator is driving valid data onto the data bus. during a read, its assertion indicates that the initiator is ready to accept data from the currently- addressed target. link req o 8 pci/cardbus 5/3.3 bus_master request indicates to the bus arbiter that this device wants to become a bus master. link gnt i 7 - 5/3.3 bus_master grant indicates to this device that access to the bus has been granted. link idsel i 22 - 5/3.3 initialization device select is used as chip select for configuration read/write transaction during the phase of device initialization. if cardbus mode (card_on = 1), this pin should be pulled up to v dd . link devsel i/o 39 pci/cardbus 5/3.3 device select when actively driven, indicates that the driving device has decoded its address as the target of the current access. link stop i/o 40 pci/cardbus 5/3.3 pci stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction. link pme o 3 pci/cardbus 5/3.3 pme output for power management event. link remark *: if the link pin is pulled up, it should be connected to l_v dd .
preliminary data sheet s15306ej2v0ds 9 pd72874 (2/2) name i/o pin no. i ol volts(v) function block * clkrun i/o 2 pci/cardbus 5/3.3 pciclk running as input, to determine the status of pclk; as output, to request starting or speeding up clock. link inta o 4 pci/cardbus 5/3.3 interrupt the pci interrupt request a. link perr i/o 41 pci/cardbus 5/3.3 parity error is used for reporting data parity errors during all pci transactions, except a special cycle. it is an output when ad0 to ad31 and par are both inputs. it is an input when ad0 to ad31 and par are both outputs. link serr o 42 pci/cardbus 5/3.3 system error is used for reporting address parity errors, data parity errors during the special cycle, or any other system error where the effect can be catastrophic. when reporting address parity errors, it is an output. link prst i 5 - 5/3.3 reset pci reset link pclk i 6 - 5/3.3 pci clock 33 mhz system bus clock. link remark *: if the link pin is pulled up, it should be connected to l_v dd .
preliminary data sheet s15306ej2v0ds 10 pd72874 1.2 phy signals: (20 pins) name i/o pin no. i ol volts(v) function block * tpa0p i/o 101 - - port-1 twisted pair a positive input/output note 1 phy analog tpa0n i/o 100 - - port-1 twisted pair a negative input/output note 1 phy analog tpb0p i/o 99 - - port-1 twisted pair b positive input/output note 1 phy analog tpb0n i/o 98 - - port-1 twisted pair b negative input/output note 1 phy analog tpa1p i/o 105 - - port-2 twisted pair a positive input/output note 1 phy analog tpa1n i/o 104 - - port-2 twisted pair a negative input/output note 1 phy analog tpb1p i/o 103 - - port-2 twisted pair b positive input/output note 1 phy analog tpb1n i/o 102 - - port-2 twisted pair b negative input/output note 1 phy analog tpa2p i/o 110 - - port-3 twisted pair a positive input/output note 1 phy analog tpa2n i/o 109 - - port-3 twisted pair a negative input/output note 1 phy analog tpb2p i/o 108 - - port-3 twisted pair b positive input/output note 1 phy analog tpb2n i/o 107 - - port-3 twisted pair b negative input/output note 1 phy analog cps i 93 - - cable power status input note2 phy digital tpbias0 o 96 - - port-1 twisted pair bias voltage output note 1 phy analog tpbias1 o 97 - - port-2 twisted pair bias voltage output note 1 phy analog tpbias2 o 111 - - port-3 twisted pair bias voltage output note 1 phy analog ri0 - 91 - - resistor0 for reference current setting note 3 phy analog ri1 - 92 - - resistor1 for reference current setting note 3 phy analog xi i 87 - - x?tal xi phy analog xo o 88 - - x?tal xo phy analog notes 1. if unused port, please refer to 4.1.4 unused ports . 2. please refer to 4.1.3 cps . 3. please refer to 4.5 ri0, ri1 . remark *: if the phy digital pin is pulled up, it should be connected to p_dv dd . if the phy analog pin is pulled up, it should be connected to p_av dd . 1.3 phy control signals: (4 pins) name i/o pin no. i ol volts(v) function block * pc0 to pc2 i 70 to 72 - 3.3 power class input note 1 phy digital p_reset i 81 - - phy power on reset input note 2 phy digital notes 1. please refer to 4.3 pc0 to pc2 . 2. please refer to 4.4 p_reset . remark *: if the phy digital pin is pulled up, it should be connected to p_dv dd . 1.4 pci/cardbus select signal: (1 pin) name i/o pin no. i ol volts(v) function block * card_on i 119 - 3.3 pci/cardbus select 1:cardbus mode 0:pci bus mode link remark *: if the link pin is pulled up, it should be connected to l_v dd .
preliminary data sheet s15306ej2v0ds 11 pd72874 1.5 serial rom interface signals: (3 pins) name i/o pin no. i ol volts(v) function block * grom_sda i/o 116 6 ma 3.3 serial eeprom data input / output link grom_scl o 117 6 ma 3.3 serial eeprom clock output link grom_en i 118 - 3.3 serial eeprom enable 1: guid load enable 0: guid load disable link remark *: if the link pin is pulled up, it should be connected to l_v dd . 1.6 d3cold wake up function signals: (2 pins) name i/o pin no. i ol volts(v) function block * d3csup i 114 - 5/3.3 d3cold support 1: d3cold wake up enable 0: d3cold wake up disable link rsmrst i 74 - 5/3.3 resume reset d3cold support (114 pin) = ?1? as this mode supports d3cold wake up, rsmrst must connect system rsmrst signal. d3cold support (114 pin) = ?0? as this mode is the pd72872 compatible, rsmrst clamp to ?1?. link remark *: if the link pin is pulled up, it should be connected to l_v dd . 1.7 ic: (7 pins) name i/o pin no. i ol volts(v) function block * ic(h) i 75 - - internally connected (high clamped) link ic(l) i 76 to 78, 80, 115 - - internally connected (low clamped) - ic(n) - 85 - - internally connected (open) - remark *: if the link pin is pulled up, it should be connected to l_v dd .
preliminary data sheet s15306ej2v0ds 12 pd72874 1.8 v dd name i/o pin no. i ol volts(v) function block * pci_v dd - 19, 60 - 5/3.3 v dd for pci i/os link l_v dd - 1, 14, 25, 31, 43, 51, 64 -3.3 v dd for link digital core and link i/os to use d3cold wake up function, l_v dd must switch v dd to vaux when the system sus pend. link p_dv dd - 73, 79, 82 - 3.3 phy digital v dd phy digital p_av dd - 86, 90, 95, 112 - 3.3 phy analog v dd phy analog remark *: if the link pin is pulled up, it should be connected to l_v dd . if the phy digital pin is pulled up, it should be connected to p_dv dd . if the phy analog pin is pulled up, it should be connected to p_av dd . 1.9 gnd name i/o pin no. i ol volts(v) function block gnd - 11, 20, 30, 38, 46, 54, 61, 69, 83, 84, 89, 94, 106, 113, 120 -- gnd -
preliminary data sheet s15306ej2v0ds 13 pd72874 2. phy registers 2.1 complete structure for phy registers figure 2-1. complete structure of phy registers 01234567 0000 physical_id r ps 0001 rhb ibr gap_count 0010 extended (7) reserved total_ports 0011 max_speed reserved delay 0100 link_active contender jitter pwr_class 0101 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 reserved 0111 page_select reserved port_select 1000 register0 (page_select) 1001 register1 (page_select) 1010 register2 (page_select) 1011 register3 (page_select) 1100 register4 (page_select) 1101 register5 (page_select) 1110 register6 (page_select) 1111 register7 (page_select) table 2-1. bit field description (1/3) field size r/w reset value description physical_id 6 r 000000 physical_id value selected from self_id period. r 1 r 0 if this bit is 1, the node is root. 1: root 0: not root ps 1 r cable power status. 1: cable power on 0: cable power off rhb 1 r/w 0 root hold -off bit. if 1, becomes root at the bus reset. ibr 1 r/w 0 initiate bus reset. setting to 1 begins a long bus reset. long bus reset signal duration: 166 sec. returns to 0 at the beginning of bus reset. gap_count 6 r/w 111111 gap count value. it is updated by the changes of transmitting and receiving the phy configuration packet tx/rx. the value is maintained after first bus reset. after the second bus reset it returns to reset value. extended 3 r 111 shows the extended register map.
preliminary data sheet s15306ej2v0ds 14 pd72874 table 2-1. bit field description (2/3) field size r/w reset value description total_ports 4 r 0011 supported port number. 0011: 3 ports max_speed 3 r 010 indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 mbps delay 4 r 0000 indicate worst case repeating delay time. 144 + (delay x 20) = 144 nsec link_active 1 r/w 1 link active. 1: enable 0: disable the logical and status of this bit and lps. state will be referred to ?l bit? of self-id packet#0. the lps is a phy/link interface signal and is defined in p1394a-2000. it is an internal signal in the pd72874. contender 1 r/w 0 contender. ?1? indicate this node support bus manager function. this bit will be referred to ?c bit? of self-id packet#0. jitter 3 r 010 the difference of repeating time (max.-min.). (2+1) x 20=60 nsec pwr_class 3 r/w see description power class. please refer to ieee1394a-2000 [4.3.4.1]. this bit will be referred to pwr field of self-id packet#0. watchdog 1 r/w 0 watchdog enable. this bit serves two purposes. when set to 1, if any one port does resume, the port_event bit becomes 1. to determine whether or not an interrupt condition shall be indicated to the link. on condition of lps = 0 and watchdog = 0, lkon as interrupt of loop, pwr_fail, timeout is not output. isbr 1 r/w 0 initiate short (arbitrated) bus reset. setting to 1 acquires the bus and begins short bus reset. short bus reset signal output : 1.3 sec returns to 0 at the beginning of the bus reset. loop 1 r/w 0 loop detection output. 1: detection writing 1 to this bit clears it to 0. writing 0 has no effect. pwr_fail 1 r/w 1 power cable disconnect detect. it becomes 1 when there is a change from 1 to 0 in the cps bit. writing 1 to this bit clears it to 0. writing 0 has no effect.
preliminary data sheet s15306ej2v0ds 15 pd72874 table 2-1. bit field description (3/3) field size r/w reset value description timeout 1 r/w 0 arbitration state machine time-out. writing 1 to this bit clears it to 0. writing 0 has no effect. port_event 1 r/w 0 set to 1 when the int_enable bit in the register map of each port is 1 and there is a change in the ports connected, bias, disabled and fault bits. set to 1 when the watchdog bit is 1 and any one port does resume. writing 1 to this bit clears it to 0. writing 0 has no effect. enab_accel 1 r/w 0 enables arbitration acceleration. ack-acceleration and fly-by arbitration are enabled. 1: enabled 0: disabled if this bit changes while the bus request is pending, the operation is not guaranteed. enab_multi 1 r/w 0 enable multi-speed packet concatenation. setting this bit to 1 follows multi-speed transmission. when this bit is set to 0,the packet will be transmitted with the same speed as the first packet. page_select 3 r/w 000 select page address between 1000 to 1111. 000: port status page 001: vendor id page 111: vendor dependent page others: unused port_select 4 r/w 0000 port selection. selecting 000 (port status page) with the page_select selects the port. selecting 111 (vendor dependent page) with the page_select have to select the port 1. 0000: port 0 0001: port 1 0010: port 2 others: unused reserved - r 000? reserved. read as 0.
preliminary data sheet s15306ej2v0ds 16 pd72874 2.2 port status page (page 000) figure 2-2. port status page 01234567 1000 astat bstat child connected bias disabled 1001 negotiated_speed int_enable fault reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 2-2. bit field description field size r/w reset value description astat 2 r xx a port status value. 00: invalid, 10: ?0? 01: ?1?, 11: ?z? bstat 2 r xx b port status value. 00: invalid, 10: ?0? 01: ?1?, 11: ?z? child 1 r child node status value. 1: connected to child node 0: connected to parent node connected 1 r 0 connection status value. 1: connected 0: disconnected bias 1 r bias voltage status value. 1: bias voltage 0: no bias voltage disabled 1 r/w see description the reset value is set to 0: enabled. negotiated_ speed 3 r shows the maximum data transfer rate of the node connected to this port. 000: 100 mbps 001: 200 mbps 010: 400 mbps int_enable 1 r/w 0 when set to 1, the port_event is set to 1 if any of this port's connected, bias, disabled or fault bits change state. fault 1 r/w 0 set to 1 if an error occurs during suspend/resume. writing 1 to this bit clears it to 0. writing 0 has no effect. reserved - r 000? reserved. read as 0.
preliminary data sheet s15306ej2v0ds 17 pd72874 2.3 vendor id page (page 001) figure 2-3. vendor id page 01234567 1000 compliance_level 1001 reserved 1010 1011 1100 vendor_id 1101 1110 1111 product_id table 2-3. bit field description field size r/w reset value description compliance_level 8 r 00000001 according to ieee1394a-2000. vendor_id 24 r 00004ch company id code value, nec ieee oui. product_id 24 r product code. reserved - r 000? reserved. read as 0. 2.4 vendor dependent page (page 111 : port_select 0001) figure 2-4. vendor dependent page 01234567 1000 1001 1010 1011 1100 1101 1110 1111 reg_array table 2-4. bit field description field size r/w reset value description reg_array 64 r/w 0 this register array is possible r/w.
preliminary data sheet s15306ej2v0ds 18 pd72874 3. configuration registers 3.1 pci bus mode configuration register (card_on = low) 31 24 23 16 15 08 07 00 device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch base address 0 10h reserved 14h reserved 18h reserved 1ch reserved 20h reserved 24h reserved 28h subsystem id subsystem v endor id 2ch reserved 30h reserved cap_ptr 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch pci_ohci_control 40h reserved 44h reserved 48h reserved 4ch reserved 50h reserved 54h reserved 58h reserved 5ch power management capabilities next_item_ptr cap_id 60h reserved power management control/status 64h reserved 68h fch
preliminary data sheet s15306ej2v0ds 19 pd72874 3.1.1 offset_00 vendor id register this register identifies the manufacturer of the pd72874. the id is assigned by the pci_sig committee. bits r/w description 15-0 r constant value of 1033h. 3.1.2 offset_02 device id register this register identifies the type of the device for the pd72874. the id is assigned by nec corporation. bits r/w description 15-0 r constant value of 00f2h. 3.1.3 offset_04 command register the register provides control over the device?s ability to generate and respond to pci cycles. bits r/w description 0r i/o enable constant value of 0. the pd72874 does not respond to pci i/o accesses. 1r/w memory enable default value of 1. it defines if the pd72874 responds to pci memory accesses. this bit should be set to one upon power-up reset. 0: the pd72874 does not respond to pci memory cycles 1: the pd72874 responds to pci memory cycles 2r/w master enable default value of 1. it enables the pd72874 as bus-master on the pci-bus. 0: the pd72874 cannot generate pci accesses by being a bus-master 1: the pd72874 is capable of acting as a bus-master 3r special cycle monitor enable constant value of 0. the special cycle monitor is always disabled. 4r/w memory write and invalidate enable default value of 0. it enables memory write and invalid command generation. 0: memory write must be used 1: the pd72874, when acts as pci master, can generate the command 5r vga tm color palette invalidate enable constant value of 0. vga color palette invalidate is always disabled. 6r/w parity error response default value of 0. it defines if the pd72874 responds to perr. 0: ignore parity error 1: respond to parity error 7r stepping enable constant value of 0. stepping is always disabled. 8r/w system error enable default value of 0. it defines if the pd72874 responds to serr. 0: disable system error checking 1: enable system error checking 9r fast back-to-back enable constant value of 0. fast back-to-back transactions are only allowed to the same agent. 15-10 r reserved constant value of 000000.
preliminary data sheet s15306ej2v0ds 20 pd72874 3.1.4 offset_06 status register this register tracks the status information of pci-bus related events which are relevant to the pd72874. ?read? and ?write? are handled somewhat differently. bits r/w description 3-0 r reserved constant value of 0000. 4r new capabilities constant value of 1. it indicates the existence of the capabilities list. 6,5 r reserved constant value of 00. 7r fast back-to-back capable constant value of 1. it indicates that the pd72874, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent. 8r/w signaled parity error default value of 0. it indicates the occurrence of any ?data parity?. 0: no parity detected (default) 1: parity detected 10,9 r devsel timing constant value of 01. these bits define the decode timing for devsel. 0: fast (1 cycle) 1: medium (2 cycles) 2: slow (3 cycles) 3: undefined 11 r/w signaled target abort default value of 0. this bit is set by a target device whenever it terminates a transaction with ?target abort?. 0: the pd72874 did not terminate a transaction with target abort 1: the pd72874 has terminated a transaction with target abort 12 r/w received target abort default value of 0. this bit is set by a master device whenever its transaction is terminated with a ?target abort?. 0: the pd72874 has not received a target abort 1: the pd72874 has received a target abort from a bus-master 13 r/w received master abort default value of 0. this bit is set by a master device whenever its transaction is terminated with ?master abort?. the pd72874 asserts ?master abort? when a transaction response exceeds the time allocated in the latency timer field. 0: transaction was not terminated with a master abort 1: transaction has been terminated with a master abort 14 r/w signaled system error default value of 0. it indicates that the assertion of serr by the pd72874. 0: system error was not signaled 1: system error was signaled 15 r/w received parity error default value of 0. it indicates the occurrence of any perr. 0: no parity error was detected 1: parity error was detected
preliminary data sheet s15306ej2v0ds 21 pd72874 3.1.5 offset_08 revision id register this register specifies a revision number assigned by nec corporation for the pd72874. bits r/w description 7-0 r default value of 01h. it specifies the silicon revision. it will be incremented for subsequent silicon revisions. 3.1.6 offset_09 class code register this register identifies the class code, sub-class code, and programming interface of the pd72874. bits r/w description 7-0 r constant value of 10h. it specifies an ieee1394 ohci-compliant host controller. 15-8 r constant value of 00h. it specifies an ?ieee1394? type. 23-16 r constant value of 0ch. it specifies a ?serial bus controller?. 3.1.7 offset_0c cache line size register this register specifies the system cache line size, which is pc-host system dependent, in units of 32-bit words. the following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. all other values will be recognized as 0, i.e. cache disabled. bits r/w description 7-0 r/w default value of 00h. 3.1.8 offset_0d latency timer register this register defines the maximum amount of time that the pd72874 is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction. bits r/w description 7-0 r/w default value of 00h. it specifies the number of pci-bus clocks that the pd72874 may hold the pci bus as a bus-master. 3.1.9 offset_0e header type register bits r/w description 7-0 r constant value of 00h. it specifies a single function device. 3.1.10 offset_0f bist register bits r/w description 7-0 r constant value of 00h. it specifies whether the device is capable of built-in self test.
preliminary data sheet s15306ej2v0ds 22 pd72874 3.1.11 offset_10 base address 0 register this register specifies the base memory address for accessing all the ?operation registers? (i.e. control, configuration, and status registers) of the pd72874, while the bios is expected to set this value during power-up reset. bits r/w description 11-0 r constant value of 000h. these bits are ?read-only?. 31-12 r/w - 3.1.12 offset_2c subsystem vendor id register this register identifies the subsystem that contains the nec?s pd72874 function. while the id is assigned by the pci_sig committee, the value should be loaded into the register from the external serial rom after power-up reset. access to this register through pci-bus is prohibited. bits r/w description 15-0 r default value of 1033h. 3.1.13 offset_2e subsystem id register this register identifies the type of the subsystem that contains the nec?s pd72874 function. while the id is assigned by the manufacturer, the value should be loaded into the register from the external serial eeprom after power-up reset. access to this register through pci-bus is prohibited. bits r/w description 15-0 r default value of 00f2h. 3.1.14 offset_34 cap_ptr register this register points to a linked list of additional capabilities specific to the pd72874, the nec?s implementation of the 1394 ohci specification. bits r/w description 7-0 r constant value of 60h. the value represents an offset into the pd72874?s pci configuration space for the location of the first item in the new capabilities linked list. 3.1.15 offset_3c interrupt line register this register provides the interrupt line routing information specific to the pd72874, the nec?s implementation of the 1394 ohci specification. bits r/w description 7-0 r/w default value of 00h. it specifies which input of the host system interrupt controller the interrupt pin of the pd72874 is connected to.
preliminary data sheet s15306ej2v0ds 23 pd72874 3.1.16 offset_3d interrupt pin register this register provides the interrupt line routing information specific to the pd72874, the nec?s implementation of the 1394 ohci specification. bits r/w description 7-0 r constant value of 01h. it specifies pci inta is used for interrupting the host system. 3.1.17 offset_3e min_gnt register this register specifies how long of a burst period the pd72874 needs, assuming a clock rate of 33 mhz. resolution is in units of ? s. the value should be loaded into the register from the external serial eeprom upon power-up reset, and access to this register through pci-bus is prohibited. bits r/w description 7-0 r default value of 00h. its value contributes to the desired setting for latency timer value. 3.1.18 offset_3f max_lat register this register specifies how often the pd72874 needs to gain access to the pci-bus, assuming a clock rate of 33 mhz. resolution is in units of ? s. the value should be loaded into the register from the external serial eeprom after hardware reset, and access to this register through pci-bus is prohibited. bits r/w description 7-0 r default value of 00h. its value contributes to the desired setting for latency timer value. 3.1.19 offset_40 pci_ohci_control register this register specifies the control bits that are ieee1394 ohci specific. vendor options are not allowed in this register. it is reserved for ohci use only. bits r/w description 0r/w pci global swap default value of 0. when this bit is 1, all quadrates read from and written to the pci interface are byte swapped, thus a ?pci global swap?. pci addresses for expansion rom and pci configuration registers, are, however, unaffected by this bit. this bit is not required for motherboard implementations. 31-1 r reserved constant value of all 0. 3.1.20 offset_60 cap_id & next_item_ptr register the cap_id signals that this item in the linked list is the registers defined for pci power management, while the next_item_ptr describes the location of the next item in the pd72874?s capability list. bits r/w description 7-0 r cap_id constant value of 01h. the default value identified the link list item as being the pci power management registers, while the id value is assigned by the pci sig. 15-8 r next_item_ptr constant value of 00h. it indicated that there are no more items in the link list.
preliminary data sheet s15306ej2v0ds 24 pd72874 3.1.21 offset_62 power management capabilities register this is a 16-bit read-only register that provides information on the power management capabilities of the pd72874. bits r/w description 2-0 r version constant value of 010. the power management registers are implemented as defined in revision 1.1 of pci bus power management interface specification. 3r pme clock constant value of 0. 4r reserved constant value of 0. 5r dsi constant value of 0. 8-6 r auxiliary power default value of 000. this field reports the vaux power requirements for the pd72874. this data is programable from eeprom. 111 ? 375 ma maximum current required for a 3.3 vaux, 110 ? 320 ma maximum current required for a 3.3 vaux, 101 ? 270 ma maximum current required for a 3.3 vaux, 100 ? 220 ma maximum current required for a 3.3 vaux, 011 ? 160 ma maximum current required for a 3.3 vaux, 010 ? 100 ma maximum current required for a 3.3 vaux, 001 ? 55 ma maximum current required for a 3.3 vaux, 000 ? 0 (self powered) 9r d1_support constant value of 1. the pd72874 supports the d1 power management state. 10 r d2_support constant value of 1. the pd72874 supports the d2 power management state. 15-11 r pme_support d3sup = ?high? : constant value of 11111. d3sup = ?low? : constant value of 01111. this field indicates the power states in which the pd72874 may assert pme. a value of ?0? for any bit indicates that the function is not capable of asserting the pme signal while in that power state. bit (11) ? pme_d0. pme can be asserted from d0. bit (12) ? pme_d1. pme can be asserted from d1. bit (13) ? pme_d2. pme can be asserted from d2. bit (14) ? pme_d3hot. pme can be asserted from d3hot. bit (15) ? pme_d3cold. pme can be asserted from d3cold.
preliminary data sheet s15306ej2v0ds 25 pd72874 3.1.22 offset_64 power management control/status register this is a 16-bit register that provides control status information of the pd72874. bits r/w description 1,0 r/w powerstate default value is undefined. this field is used both to determine the current power state of the pd72874 and to set the pd72874 into a new power state. 00: d0 (dma contexts: on, link layer: on, pme will be asserted upon inta being active.) 01: d1 (dma contexts: off, link layer: on, pme will be asserted upon inta being active) 10: d2 (dma contexts: off, link layer: off, lps: off, pme will be asserted upon linkon being active) 11: d3 (dma contexts: off, link layer: off, lps: off, pme will be asserted upon linkon being active) the lps is a phy/link interface signal and is defined in p1394a-2000. it is an internal signal in the pd72874. 7-2 r reserved constant value of 000000. 8r/w pme_en default value of 0. this field is used to enable the specific power management features of the pd72874. 12-9 r data_select constant value of 0000. 14,13 r data_scale constant value of 00. 15 r/w pme_status default value is undefined. a write of ?1? clears this bit, while a write of ?0? is ignored.
preliminary data sheet s15306ej2v0ds 26 pd72874 3.2 cardbus mode configuration register (card_on = high) 31 24 23 16 15 08 07 00 device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch base address 0 10h base address 1 (cardbus status reg) note 14h base address 2 (cardbus status reg) note 18h reserved 1ch reserved 20h reserved 24h cardbus cis pointer note 28h subsystem id subsystem v endor id 2ch reserved 30h reserved cap_ptr 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch pci_ohci_control 40h reserved 44h reserved 48h reserved 4ch reserved 50h reserved 54h reserved 58h reserved 5ch power management capabilities next_item_ptr cap_id 60h reserved power management control/status 64h reserved 68h reserved 6ch reserved 70h reserved 74h reserved 78h reserved 7ch cis area note 80h fch note different from pci bus mode configuration register.
preliminary data sheet s15306ej2v0ds 27 pd72874 3.2.1 offset_14/18 base address 1/2 register (cardbus status registers) bits r/w description 7-0 r constant value of 00. 31-8 r/w - (1) function event register (fer) (base address 1 (2) + 0h) bits r/w description 0 r write protect (no use). read only as ?0? 1 r ready status (no use). read only as ?0? 2 r battery voltage detect 2 (no use). read only as ?0? 3 r battery voltage detect 1 (no use). read only as ?0? 4 r/w general wake up 14-5 r reserved. read only as ?0? 15 r/w interrupt 31-16 r reserved. read only as ?0? (2) function event mask register (femr) (base address 1 (2) + 4h) bits r/w description 0 r write protect (no use). read only as ?0? 1 r ready status (no use). read only as ?0? 2 r battery voltage detect 2 (no use). read only as ?0? 3 r battery voltage detect 1 (no use). read only as ?0? 4 r/w general wake up mask 5 r bam. read only as ?0? 6 r pwm. read only as ?0? 13-7 r reserved. read only as ?0? 14 r/w wake up mask 15 r/w interrupt 31-16 r reserved. read only as ?0?
preliminary data sheet s15306ej2v0ds 28 pd72874 (3) function reset status register (frsr) (base address 1 (2) + 8h) bits r/w description 0 r write protect (no use). read only as ?0? 1 r ready status (no use). read only as ?0? 2 r battery voltage detect 2 (no use). read only as ?0? 3 r battery voltage detect 1 (no use). read only as ?0? 4 r/w general wake up mask 14-5 r reserved. read only as ?0? 15 r/w interrupt 31-16 r reserved. read only as ?0? (4) function force event register (ffer) (base address 1 (2) + ch) bits r/w description 0 r write protect (no use). read only as ?0? 1 r ready status (no use). read only as ?0? 2 r battery voltage detect 2 (no use). read only as ?0? 3 r battery voltage detect 1 (no use). read only as ?0? 4 r/w general wake up mask 14-5 - no use 15 r/w interrupt 31-16 r reserved. read only as ?0? 3.2.2 offset_28 cardbus cis pointer this register specifies start memory address of the cardbus cis area. bits r/w description 31-0 r starting pointer of cis area. constant value of 00000080h. 3.2.3 offset_80 cis area the pd72874 supports external serial rom (at24c02 compatible) interface. cis area register can be loaded from external serial rom in the cis area when card_on is 1.
preliminary data sheet s15306ej2v0ds 29 pd72874 4. phy function 4.1 cable interface 4.1.1 connections figure 4-1. cable interface + - + - + - + - + - + - 56 ? 56 ? 7 k ? 7 k ? connection detection current connection detection comparator tpap tpbias tpan driver receiver arbitration comparators common mode comparators + - + - + - + - 56 ? 56 ? 7 k ? 7 k ? tpbp tpbn driver receiver arbitration comparators common mode comparator common mode speed current driver 1 f 270 pf 5.1 k ? + - + - + - + - + - + - 56 ? 56 ? 7 k ? 7 k ? connection detection current connection detection comparator tpap tpbias tpan driver receiver arbitration comparators common mode comparators 1 f + - + - + - + - 56 ? 56 ? 7 k ? 7 k ? tpbp tpbn driver receiver arbitration comparators common mode comparator common mode speed current driver 270 pf 5.1 k ? 0.01 f 0.01 f
preliminary data sheet s15306ej2v0ds 30 pd72874 4.1.2 cable interface circuit each port is configured with two twisted-pairs of tpa and tpb. tpa and tpb are used to monitor the state of the transmit/receive line, control signals, data and cables. during transmission to the ieee1394 bus, the data/strobe signal received from the link layer controller is encoded, converted from parallel to serial and transmitted. while receiving from the ieee1394 bus, the data/strobe signal from tpa, tpb is converted from serial to parallel after synchronization by sclk note , then transmitted to the link layer controller in 2/4/8 bits according to the data rate of 100/200/400 mbps. the bus arbitration for tpa and tpb and the state of the line are monitored by the built-in comparator. the state of the 1394 bus is transmitted to the state machine in the lsi. note the sclk is a phy/link interface signal and is defined in p1394a-2000. it is an internal signal in the pd72874. 4.1.3 cps connect an external resistor of 390 k ? between the cps pin and the power cable, and an external resistor of 100 k ? between the cps pin and the gnd to monitor the power of the power cable. if the cable power falls under 7.5 v there is an indication to the link layer that the power has failed. 4.1.4 unused ports tpap, tpan : not connected tpbp, tpbn : agnd tpbias : not connected 4.2 pll and crystal oscillation circuit 4.2.1 crystal oscillation circuit to supply the clock of 24.576 mhz 100 ppm, use an external capacitor of 10 pf and a crystal of 50 ppm. 4.2.2 pll the crystal oscillator multiplies the 24.576 mhz frequency by 16 (393.216 mhz). 4.3 pc0 to pc2 the pc0 to pc2 pin corresponds to the power field of the self_id packet and pwr_class in the phy register. refer to section 4.3.4.1 of the ieee1394-1995 specification for information regarding the pwr_class. the value of pwr can be changed with software through the link layer; this pin sets the initial value during power-on reset. use a pull-up or pull-down resistor of 1 k ? based on the application. 4.4 p_reset connect an external capacitor of 0.1 f between the pins p_reset and gnd. if the voltage drops below 0 v, a reset pulse is generated. all of the circuits are initialized, including the contents of the phy register. 4.5 ri0, ri1 connect an external resistor of 9.1 k ? 0.5 % to limit the lsi?s current.
preliminary data sheet s15306ej2v0ds 31 pd72874 5. electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ?0.5 to +4.6 v lvttl @ (v i < 0.5 v + v dd ) ?0.5 to +4.6 v input voltage v i pci @ (v i < 3.0 v + v dd ) ?0.5 to +6.6 v lvttl @ (v o < 0.5 v + v dd ) ?0.5 to +4.6 v output voltage v o pci @ (v o < 3.0 v + v dd ) ?0.5 to +6.6 v operating ambient temperature t a 0 to +70 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating ranges parameter symbol condition rating unit used to clamp reflection on pci bus. 4.5 to 5.5 v power supply voltage v dd 3.0 to 3.6 v operating ambient temperature t a 0 to +70 c
preliminary data sheet s15306ej2v0ds 32 pd72874 dc characteristics (v dd = 3.3 v 10 %, v ss = 0 v, t a = 0 to +70 c) parameter symbol condition min. typ. max. unit high-level input voltage v ih 2.0 v dd +0.5 v low-level input voltage v il ?0.5 +0.8 v high-level output current i oh v oh = 2.4 v, grom_sda, grom_scl ?6 ma low-level output current i ol v ol = 0.4 v, grom_sda, grom_scl 6ma input leakage current i l v in = v dd or gnd 10.0 a pci interface high-level input voltage v ih 2.0 5.5 v low-level input voltage v il ?0.5 +0.8 v high-level output current i oh v oh = 2.4 v ?2 ma low-level output current i ol v ol = 0.4 v 9 ma input leakage current i l v in = v dd or gnd 10.0 a cable interface cable input, 100 mbps operation 142 260 mv cable input, 200 mbps operation 132 260 mv differential input voltage v id cable input, 400 mbps operation 118 260 mv 100 mbps speed signaling off 1.165 2.515 v 200 mbps speed signaling 0.935 2.515 v tpb common mode input voltage v icm 400 mbps speed signaling 0.523 2.515 v differential output voltage v od cable output (test load 55 ? ) 172.0 265.0 mv 100 mbps speed signaling off 1.665 2.015 v 200 mbps speed signaling 1.438 2.015 v tpa common mode output voltage v ocm 400 mbps speed signaling 1.030 2.015 v 100 mbps speed signaling off ?0.81 +0.44 ma 200 mbps speed signaling ?4.84 ?2.53 ma tpa common mode output current i cm 400 mbps speed signaling ?12.40 ?8.10 ma power status threshold voltage v th cps 7.5 v tpbias output voltage v tpbias 1.665 2.015 v remarks 1. digital core runs at 3.3 v. 2. pci interface can run at 5 or 3.3 v, depending on the choice of 5 v-pci or 3.3 v-pci. 3. all other i/os are 3.3 v driving, and 5 v tolerant. 4. 5 v are used only for 5 v-pci clamping diode. 3.3 v protection circuit 5.0 v i/o buffer
preliminary data sheet s15306ej2v0ds 33 pd72874 ac characteristics pci interface see pci local bus specification revision 2.2. serial rom interface see at24c01a/02/04/08/16 spec. sheet.
preliminary data sheet s15306ej2v0ds 34 pd72874 6. package drawing 90 60 61 120 1 31 30 91 s 120-pin plastic tqfp (fine pitch) (14x14) item millimeters i j 0.40 (t.p.) 0.07 a 16.00 0.20 f 1.20 g h 0.18 0.05 1.20 k 1.00 0.20 s 1.20max. r3 t 0.25 + 4 ? 3 r h k l j f n q m g i a b cd sm t u s p detail of lead end note each lead centerline is located within 0.07 mm of its true position (t.p.) at maximum material condition. b 14.00 0.20 c d 16.00 0.20 14.00 0.20 l 0.50 m 0.17 + 0.03 ? 0.07 n 0.08 p 1.00 0.05 q 0.10 0.05 p120gc-40-yeb
preliminary data sheet s15306ej2v0ds 35 pd72874 7. recommended soldering conditions the pd72874 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 7-1. surface mounting type soldering conditions pd72874gc-yeb: 120-pin plastic tqfp (fine pitch) (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher). count: three times or less exposure limit: 3 days note (after that prebake at 125 c for 10 hours) ir35-103-3 partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
preliminary data sheet s15306ej2v0ds 36 pd72874 [memo]
preliminary data sheet s15306ej2v0ds 37 pd72874 [memo]
preliminary data sheet s15306ej2v0ds 38 pd72874 [memo]
preliminary data sheet s15306ej2v0ds 39 pd72874 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd72874 eeprom and firewarden are trademarks of nec corporation. vga is a trademark of ibm corporation. m8e 00. 4 the information in this document is current as of april, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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